1. Field of the Invention
The invention relates to electronic device wafer level packages, and more particularly to CMOS image sensing device wafer level packages and fabrication methods thereof.
2. Description of the Related Art
CMOS image sensors are used in a wide variety of applications, such as digital still cameras (DSC). These devices utilize an array of active pixels or image sensor cells, comprising photodiode elements, to receive electromagnetic radiation to convert images to streams of digital data.
Chip scale packages (CSPs) are designed for flip chip bonding to a supporting substrate, such as a package substrate, a module substrate or a printed circuit board (PCB). With flip chip bonding, bumps, pins or other terminal contacts on the package, are bonded to mating contacts on the supporting substrate. The bonded terminal contacts provide the physical and electrical connections between the package and the supporting substrate.
To solve bonding connection problems, a shellcase semiconductor device chip scale packaging technique has been developed. For example, U.S. Pat. No. 6,792,480, and U.S. Pub. No. 2001/0018236, the entireties of which are hereby incorporated by references, disclose semiconductor chip scale packaging techniques. T-shaped connections between the substrate bonding contact and the die bonding contacts are provided. FIG. 1A is a cross section illustrating a conventional CMOS image sensing device wafer level package. FIG. 1B is an enlarged view of region 1B of FIG. 1A. Referring to FIG. 1A, a CMOS image sensing package includes a transparent substrate 24 configured as a support structure for a chip scale package. A CMOS image sensor die 12 with a die circuitry is attached on the transparent substrate 24. The CMOS image sensor die 12 comprises a sensor area with a micro-lens array 10 configured as an image sensing plane. A spacer 26 is disposed between the transparent substrate 24 and the CMOS image sensor die 12 defining a cavity 30. Encapsulant layers 14 and 28 are formed on the substrate encapsulating the CMOS image sensor die 12. An optical structure 16 is disposed on the encapsulant layer 14 to strengthen the chip scale package. One end of a T-shaped connection 18 extends from the die circuitry to a plurality of terminal contacts of the chip scale package, while another end of the T-shaped connection 18 connects to contact pads 22. A ball grid array 20 is formed on the terminal contacts of the chip scale package.
Referring to FIG. 1B, the contact area 18a between the T-shaped connection 18 and contact pads 22 is so small that weak spots are vulnerable to peeling and low reliability.
Accordingly, there is a market demand for an electronic device chip scale package design, whereby conductivity and adhesion between the T-shaped connection and contact pads are ameliorated.